On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits1
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منابع مشابه
On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI...
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---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-ha...
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{ Until recently, VLSI designers rarely considered yield issues when selecting a oorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the oorplan can aaect the projected yield. We study several general oorplan structures, make some speciic recommendations, and apply them to actual VLSI chips...
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